This invention relates to magnetic device structures in monolithic integrated circuits and, more particularly, to the interconnection of such magnetic device structures and other portions of the integrated circuit.
Digital memories for digital systems of various kinds can be advantageously based on the storage of digital bits as alternative states of magnetization in ferromagnetic thin film materials used to provide each memory storage cell. Access to the information stored in such memory cells can be provided by using magnetoresistive sensing to determine the magnetization state in the material. Such ferromagnetic thin film memories can be provided on the surface of a monolithic integrated circuit to permit convenient electrical interconnections between the memory cell containing such ferromagnetic thin film material, and the memory operating circuitry.
Ferromagnetic thin film memory cells are usually made very small and packed very closely together to achieve a significant density of stored bits, particularly when provided on a surface in a monolithic integrated circuit. The magnetic environment thereabout can become quite complex with fields in any one memory cell affecting the film portions in neighboring memory cells. Also, small ferromagnetic film portions in a memory cell can lead to substantial demagnetizing fields which can cause instabilities in the magnetization state desired in such a cell in the storage of information therein.
These magnetic effects between neighbors in an array of closely packed ferromagnetic thin film memory cells can be ameliorated to a considerable extent by providing a memory cell based on an intermediate separating material having two major surfaces on each of which a magnetoresistive, anisotropic ferromagnetic memory film is provided. Such an arrangement provides significant "flux closure" to thereby confine the magnetic fields arising in a cell to affecting primarily just that cell. This is considerably enhanced by choosing the separating material in the ferromagnetic memory film to be sufficiently thin.
Often such a digital memory is constructed by having a number of memory cell storage structures (or bit structures if there is a single structure per bit), at which magnetic interactions occur in storing or obtaining information therein, connected in series at junctures to one another in an end-to-end fashion. A series of current straps, or word lines, are often provided in an orthogonal layout to the series of connected storage structures so that a strap crosses each of the structures between the junctures therein. In a magnetoresistive memory, such straps or word lines are used both in the entering of and the sensing of information in the bit structures. This can be done by using currents in the word lines for setting, or for determining the existing, magnetization state of storage structures in the memory.
However, with respect to magnetic fields generated by word lines over a storage structure there is no "flux closure." This is because the word line is over the top of the bit structure so that there is no closed magnetic path or magnetic fields in the structure around the word line. The result is that very large demagnetizing fields can occur in the bit structure both for entering information and for sensing information in that structure. Such fields can seriously disrupt operation of the memory.
These demagnetizing fields can be reduced by properly constructing such bit structures, providing a narrowing geometry or taper toward the ends of the structures where they come to the junctures. A narrowed portion of magnetic material may extend entirely through a juncture between storage structures.
With such magnetic structure arrangements, the resultant magnetization of bit or storage structures becomes more stable giving better defined alternative magnetization states for storing digital information. In those memory cell structures from which such information is to be extracted by use of the magnetoresistive properties to assess which of these magnetization states occurs in the ferromagnetic memory films, some sort of sensing current is applied through the storage structures in addition to that supplied through the word lines.
Storage structures formed as bit structures, each being in one of two alternate magnetization states typified by having the magnetization vector point in one of two approximately opposite directions more or less along the easy axis, will have correspondingly different resistances at least during a reading operation depending on which magnetization state such structure is in. A sense current provided through the structure will then lead to different voltage drops across the structure depending on its magnetization state thereby providing the information as to the state it is in. Alternatively, a sensing voltage could be applied to such bit structures with the resulting current differences, because of their resistance differences, indicating which magnetization state is present in a bit structure.
The signal information contained in either of these differing voltage drops, or these differing current flows, must be sensed and then provided to other portions of the circuitry for transmitting and using this information. Such sensing, transmitting and using is accomplished in circuitry provided in the monolithic integrated circuit outside of, and supporting, the memory cell array. Thus, connections must be made to the series of connected bit structures, or storage structures, located in the monolithic integrated circuit outside of the array. Heretofore, this has been done through the provision of a metallization interconnection system that is placed in contact with the series connected bit structure arrangement through an opening in an overlying protective layer, this metallization interconnection then being extended over the protective layer to another opening therein. There it is placed in contact with a circuit component in the circuitry outside the array. The provision of such a metallization interconnection requires additional processing steps after provision of the bit structures. These processing steps require certain tolerances to provide reliable results which lead to the metallization interconnection taking additional space to provide sufficient tolerances to assure that electrical contact is made to the bit structures.
Thus, an interconnection arrangement which can reduce the number of processing steps required is desirable to reduce costs and improve reliability. Further, an arrangement which minimizes the space required for interconnections between the memory cell array and circuitry external thereto will also reduce cost through increasing the density of circuitry per unit area in the monolithic integrated circuit.